There is an interface that sends and receives image data using a synchronizing clock, an effective pixel signal indicating the timing of effective pixels in image data, and image data. An example is described below in which image processing apparatuses having such interfaces are connected to each other. For instance, in a case where a first image processing apparatus that outputs an effective pixel signal for each line at discrete timings is connected to a second image processing apparatus that requires a continuous effective pixel signal for each line and recognizes as a line interval when the effective pixel signal is not asserted and image data is transmitted from the first image processing apparatus to the second image processing apparatus, a line buffer for storing a single line of image data needs to be provided therebetween. Specifically, the line buffer stores a single line of image data that is output from the first image processing apparatus in accordance with a discrete effective pixel signal. The stored single line of image data is then supplied together with a continuous effective pixel signal to the second image processing apparatus. Such a conventional method using a line buffer requires a line buffer for storing a single line of image data and thus faces the challenge of increased cost.
Meanwhile, Japanese Patent Laid-Open No. 2003-087639 has proposed a technique in which, when image processing apparatuses are connected, a signal that is obtained by taking a logical OR of a delayed effective pixel signal and an original effective pixel signal is used as a clock gate, thereby reducing power consumption during time periods when image data is not effective.
Following is a description of the challenges to be faced when the technique disclosed in Japanese Patent Laid-Open No. 2003-087639 is used in order to connect the aforementioned first and second image processing apparatuses.
FIG. 1 is a diagram illustrating an example where the method described in Japanese Patent Laid-Open No. 2003-087639 is applied to a case where four clocks (four cycles) are necessary for subsequent image processing in the first image processing apparatus that outputs a discrete effective pixel signal.
A clock signal 100 is always output as a synchronizing clock. Reference numeral 101 denotes an effective pixel signal that is high-level at the timings of effective pixels in image data. Reference numeral 102 denotes a delayed effective pixel signal that is obtained by delaying the effective pixel signal 101 by four clock cycles, which is necessary for image processing. A gate signal 103 is generated by taking a logical OR of the effective pixel signal 101 and the delayed effective pixel signal 102. Reference numeral 104 denotes a clock signal that is obtained by gating the clock signal 100 with the gate signal 103. Reference numeral 105 denotes image data that is indicated as being effective by the gated clock signal 104. The subsequent image processing apparatus uses the gated clock signal 104 as a clock to process parts of the image data 105 where the effective pixel signal 101 is effective.
The subsequent image processing apparatus can obtain effective image data 105 at a leading edge 110 of the gated clock signal 104 obtained as described above in Japanese Patent Laid-Open No. 2003-087639, where the effective pixel signal 101 is effective. However, image data that is not effective is input at a leading edge 111 because the effective pixel signal 101 is not effective. In addition, although four clock cycles are needed at the back end of each line, the gated clock signal 104 has less than four cycles at the back end of line. That is, there is no fourth clock that is needed at a fourth cycle time at the timing 112. This shows the problems that an extra clock edge is generated at the leading edge 111 and no clock is generated at the timing 112. In other words, the challenge faced is that the method disclosed in Japanese Patent Laid-Open No. 2003-087639 cannot be applied as-is to cases where an image processing apparatus that outputs the discrete effective pixel signal is connected to an image processing apparatus that requires the continuous effective pixel signal.